IC’Alps and ENSTA Bretagne announced today successful implementation of an embedded FPGA (eFPGA) core on silicon. The development of this eFPGA is the result of a research program funded with the support of the European Union, Region Bretagne and local authorities, with the objective of strengthening the technical competencies of ENSTA Bretagne in the field of cyber defence.
An embedded FPGA (eFPGA) is a programmable IP core integrated into SoCs or custom ICs (ASIC). eFPGA technology is winning converts among system architects because market requirements are constantly changing and integrated circuits are becoming increasingly complex and expensive to develop. “Adding eFPGA functionality to ASIC designs brings the flexibility and performance of programmable logic without the cost, but with better power, performance, throughput and latency”, said Théotime Bollengier, IC architect at ENSTA Bretagne.
ENSTA Bretagne eFPGA includes the following features:
• 3200 4-inputs look-up tables (LUTs)
• Standard cell based to enable seamless generation from an RTL netlist
• Technology independent core (standard cell based)
• Fully integrated into standard RTL design flows
• Generated and programmed with ENSTA’s ArGen framework
IC’Alps was handed the responsibility of silicon implementation and prototyping, both needed to make a first demonstrator of ENSTA’s technology. The company was in charge of IC definition, foundry process selection, design (synthesis, floorplan, IO ring, place & route), design for testability, post layout simulations and verifications before launch in fabrication. IC’Alps took in charge the required supply chain management including selection of partners, fabrication, and package assembly.
“This integrated circuit made for ENSTA Bretagne is a proof of our expertise in digital physical implementation and our capability to set up and manage a complete supply chain”, said Jean-Luc Triouleyre, CEO of IC’Alps. “Our Team has supported ENSTA-Bretagne from ASIC specification, reached tape-out and delivered packaged dies on-time, even during this COVID period. Last but not least, the team demonstrated its implication to reach first silicon good silicon”.
IC’Alps’ approach to collaborative working has given ENSTA Bretagne flexibility (inputs, implementation flow) and the security of opened discussions. A synergy of expertise has been an important factor to beat the challenge of quick realization of a functional first-silicon demonstrator. “We are happy to announce that the first demonstrator in TSMC 55 nm ULP process technology is back from fab and tested fully functional”, added Loïc Lagadec and Jean-Christophe Le Lann, both researchers at ENSTA Bretagne.